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INTEGRATED CIRCUITS
74F552 Octal registered transceiver with parity and flags (3-State)
Product specification IC15 Data Handbook 1991 Jan 02
Philips Semiconductors
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
FEATURES
* 8-bit bidirectional I/O port with handshake * Register status flag flip-flops * Separate clock enable and output enable * Parity generation and parity check * B outputs and parity output sink 64mA
DESCRIPTION
The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the Output Enable returns to High after reading the output port. Each register has a separate Output Enable (OEAS, OEBR) for its 3-State buffer. The separate Clocks, Flags and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A port to the B port, a parity bit is generated. On the other hand, when data is transferred from the B port to the A port, the parity of input data on B0-B7 is checked. TYPICAL SUPPLY CURRENT (TOTAL) 120mA
PIN CONFIGURATION
B4 1 B5 B6 B7 OEBR CPR CER VCC ERROR 2 3 4 5 6 7 8 9 28 B3 27 B2 26 B1 25 B0 24 FR 23 PARITY 22 GND 21 CES 20 CPS 19 OEAS 18 A0 17 A1 16 A2 15 A3
FS 10 A7 11 A6 12 A5 13 A4 14
SF01039
LOGIC SYMBOL (IEEE/IEC)
XCVR 6 7 5 20 21 19 1C2 EN1' EN6 6C4 EN3 EN6 Z7 6 6,7 5 9 10 14 5,6 5,6 23
TYPE 74F552
TYPICAL fMAX 85MHz
ORDERING INFORMATION
DESCRIPTION 28-Pin Plastic DIP (600mil) 28-Pin Plastic SOL COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F552N N74F552D
18 3,4,6 1,2,6 25 26 27 28 1 2 3 4
PKG DWG #
17
SOT117-2 SOT136-1
16 15 14 13 12
LOGIC SYMBOL
18 17 16 15 14 13 12 11
11 A0 6 7 21 20 19 5 CPR CER CES CPS OEAS OEBR B0 B1 B2 B3 B4 B5 PARITY FS FR ERROR 23 10 24 9 A1 A2 A3 A4 A5 A6 A7
SF01040
B6
B7
VCC = Pin 8 GND = Pin 22
25
26
27
28
1
2
3
4
SF01041
1991 Jan 02
2
853-1098 01347
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS A0-A7 B0-B7 CPR CPS CER CES OEBR OEAS A Data inputs B Data inputs R registers clock input (active rising edge) S registers clock input (active rising edge) R registers clock Enable input (active Low) S registers clock Enable input (active Low) A-to-B Output Enable input (active Low) and clear FS output (active Low) B-to-A Output Enable input (active Low) and clear FR output (active Low) Parity bit transceiver input PARITY Parity bit transceiver output ERROR A0-A7 B0-B7 FR FS Parity check output (active Low) A Data outputs B Data outputs A-to-B Status Flag output (active High) B-to-A Status Flag output (active High) 750/106.7 50/33.3 150/40 750/106.7 50/33.3 50/33.3 15mA/64mA 1.0mA/20mA 3.0mA/24mA 15mA/64mA 1.0mA/20mA 1.0mA/20mA DESCRIPTION 74F(U.L.) HIGH/LOW 3.5/1.0 3.5/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/2.0 3.5/1.0 LOAD VALUE HIGH/LOW 70A/0.6mA 70A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/1.2mA 20A/1.2mA 70A/0.6mA
NOTE: One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state.
FUNCTIONAL DESCRIPTION
Data applied to the A inputs are entered and stored on the rising edge of the CPR clock pulse, provided that the CER is Low; simultaneously, the status flip-flop is set and the A-to-B flag (FR) output goes High. As the CER returns to High, the data will be held in R register. This data entered from the A inputs will appear at the B port I/O pins after the OEBR has gone Low. When OEBR is Low, a parity bit appears at the PARITY pin, which will be set High when there is an even number of 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR, by changing the signal at the OEBR pin from Low to High. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A Low at the CES pin and a Low-to-High transition at the CPS pin enters the B input data and the parity input data into the S register and the parity register respectively and set the flag output FS to High. A Low signal at the OEAS pin enables the A port I/O pins and a Low-to-High transition of the OEAS signal clears the FS flag. When OEAS is Low, the parity check output ERROR will be High if there is an odd number of 1s at the Q outputs of the S register and the parity register.
R or S REGISTER FUNCTION TABLE
INPUTS An or Bn X L H H= L= NC= X= X= = = CPX X CEX H L L OUTPUTS INTERNAL Q NC L H NC OPERATING MODE Hold data Load data Keep old data
X L High voltage level Low voltage level No change Don't care R or S for CPX and CEX Low-to-High transition Not Low-to-High transition
OUTPUT CONTROL TABLE
INPUT OEXX H OUTPUTS INTERNAL Q X An or Bn Z L H OPERATING MODE Disable outputs Enable outpus
H= L= X= XX= Z=
L L L H High voltage level Low voltage level Don't care AS or BR High impedance "off" state
1991 Jan 02
3
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
R or S FLAG FUNCTION TABLE
INPUTS CEX H L CPX X OEXX OUTPUTS FR or FS NC H L OPERATING MODE Hold flag Set flag Clear flag
PARITY GENERATION FUNCTION TABLE
INPUTS OEBR H L L = = = = = CPR X OUTPUTS Number of Highs in the Q outputs of the R register X PARITY Z H L OPERATING MODE Hold flag Load data
X X H = High voltage level L = Low voltage level NC= No change X = Don't care X = R or S for CPX and CEX XX= AS or BR = Low-to-High transition = Not Low-to-High transition
H L X Z
0,2,4,6,8 1,3,5,7 High voltage level Low voltage level Don't care High impedance "off" state Low-to-High transition
PARITY CHECK FUNCTION TABLE
INPUTS OEAS H L L L L H L X = = = = CPS X PARITY X L L H H OUTPUTS Number of Highs in the Q outputs of the R register X 0,2,4,6,8 1,3,5,7 0,2,4,6,8 1,3,5,7 ERROR H L H H L OPERATING MODE
Parity check
High voltage level Low voltage level Don't care Low-to-High transition
1991 Jan 02
4
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
LOGIC DIAGRAM
CES 21
CPS 20
DETAIL A DETAIL B CER 7 D CPR 6 CP Q Q
23
PARITY
Q A0 18 Q
D SEL SEL CP DETAIL B
25
B0
DETAIL A DETAIL B A1 17 DETAIL A D O SEL SEL CP Q DETAIL A
26
B1
27
B2
A2
16
28 B3 DETAIL B
A3 15 DETAIL A
1
B4
A4 14 2 DETAIL A B5
A5
13
9
ERROR
DETAIL A 3 A6 12 DETAIL A DETAIL B B6
4
B7
A7
11
OEBR 5
D CP
Q 24 FR
CLR Q OEAS 19 D CP CLR Q VCC = GND = Pin 8 Pin 22 Q 10 FS
SF01042
1991 Jan 02
5
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT Supply voltage Input voltage Input current Voltage applied to output in High output state FR, FS, ERROR IOUT Tamb Tstg Current applied to output in Low output state A0-A7 B0-B7, PARITY Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +VCC -0.5 to +VCC 40 48 128 0 to +70 -65 to +150 UNIT V V mA V mA mA mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK Supply voltage High-level input voltage Low-level input voltage Input clamp current FR, FS, ERROR IOH High-level output current A0-A7 B0-B7, PARITY FR, FS, ERROR IOL Tamb Low-level output current A0-A7 B0-B7, PARITY Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -1 -3 -15 20 24 64 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA mA mA mA mA C
1991 Jan 02
6
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG MIN 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC 2.5 2.7 2.4 2.7 2.0 2.0 0.30 0.30 0.35 0.35 0.38 0.42 -0.73 0.50 0.50 0.50 0.50 0.55 0.55 -1.2 100 1 3.3 3.4 TYP
NO TAG
UNIT MAX V V V V V V V V V V V V V A mA A mA mA A A mA mA mA mA mA
FR, FS FR FS, ERROR High-level output g voltage VCC = MIN, VIL = MAX MAX, VIH = MIN
IO = -1mA 1mA OH
VO OH
A0-A7 A0 A7
IO = -3mA 3mA OH
B0-B7, B0 B7 PARITY
IO = -15mA 15mA OH
FR. FS FR FS. ERROR Low-level output voltage VCC = MIN, VIL = MAX, MAX VIH = MIN
IO = 20mA OL
VO OL
A0-A7 A0 A7
IO = 24mA OL IOL = 48mA IOL = 64mA
B0-B7, B0 B7 PARITY VIK II Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current others A0-A7, B0-B7, PARITY others except A0-A7, B0-B7, PARITY others OEAS, OEBA A0-A7, B0-B7, B0-B7 PARITY
VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = 5.5V, VI = 5.5V
IIH
VCC = MAX, VI = 2.7V
20 -0.6
IIL IOZH+IIH IOZL+IIL
VCC = MAX, VI = 0 5V MAX 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V -60 VCC = MAX -100 115 VCC = MAX 125 120
-1.2 70 -600 -150 -225 170 185 180
Off-state output current High-level voltage applied Off-state output current Low-level voltage applied Short-circuit output currentNO TAG
IOS
A0-A7, FS, FR, ERROR B0-B7, PARITY ICCH
ICC
Supply current (total)
ICCL ICCZ
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS should be performed last.
1991 Jan 02
7
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL Maximum Clock Frequency Propagation delay CPS to An or CPR to Bn Propagation delay CPS to FS or CPR to FR Propagation delay OEAS to FS or OEBR to FR Propagation delay CPS to ERROR Propagation delay CPR to PARITY Propagation delay OEAS to ERROR Output Enable time OEAS to An or OEBR to Bn Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 4 Waveform 4 Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG 70 3.5 4.0 3.0 4.0 6.5 7.5 6.5 10.5 3.5 3.0 2.5 4.0 TYP 85 5.0 6.0 5.0 6.0 13.0 11.5 8.5 13.5 5.5 5.0 4.0 6.5 8.0 9.0 7.5 8.5 16.5 15.0 11.0 17.0 8.0 7.0 7.0 9.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 60 3.0 3.5 2.5 3.5 6.0 7.0 5.5 10.0 3.0 2.5 2.0 4.0 8.5 9.0 8.5 9.0 18.0 16.0 12.5 18.0 8.5 8.0 8.0 10.5 MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns UNIT
tPHZ tPLZ
Output Disable time OEAS to An or OEBR to Bn
2.0 2.0
4.0 3.5
7.0 7.0
1.5 1.5
8.5 7.5
ns ns
tPZH tPZL
Output Enable time OEBR to PARITY
2.0 4.0
4.0 5.5
7.0 8.0
2.0 3.0
7.5 9.0
ns ns
tPHZ tPLZ
Output Disable time OEBR to PARITY
2.0 2.0
4.0 4.0
7.0 7.5
2.0 2.0
7.5 8.0
ns ns
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tREC Setup time, High or Low An or Bn or PARITY to CPS or CPR Hold time, High or Low An or Bn or PARITY to CPS or CPR Setup time, High or Low CES to CPS or CER to CPR Hold time, High or Low CES to CPS or CER to CPR CPS or CPR Pulse width, High or Low Recovery time OEBR to CPR or OEAS to CPS Waveform 5 Waveform 5 Waveform 5 Waveform 5 Waveform 1 Waveform 6 7.5 4.5 0 0 7.0 7.0 0 0 5.0 6.5 14.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 8.5 5.5 0 0 7.5 7.5 0 0 6.5 7.5 16.5 MAX ns ns ns ns ns ns UNIT
1991 Jan 02
8
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted ot change for predictable output.
1/fMAX tW(H) CPS, CPR VM tW(L) tPLH An, Bn FS, FR tPHL VM VM FS, FR VM OEAS, OEBR VM tPHL
VM
SF01043
SF01044
Waveform 1. Propagation Delay, Clock Input to Output and Maximum Clock Frequency
Waveform 2. Propagation Delay, Output Enable to Flag Output
OEAS
VM tPHL
VM tPLH VM VM
CPS, CPR
VM
VM
tPLH PARITY VM tPHL tPLH ERROR tPHL VM VM VM
ERROR
SF01045
SF01046
Waveform 3. Propagation Delay, Output Enable to ERROR
Waveform 4. Propagation Delay, Clock to PARITY and ERROR
An, Bn CES, CER PARITY
VM ts(L)
VM th(H)
VM ts(H)
VM th(L)
OEAS, OEBR
VM tREC
CPS, CPR
VM
VM
CPS, CPR
VM
SF01047
SF01048
Waveform 5. Data Setup and Hold Times
Waveform 6. Recovery Time from Output Enable to Clock
OEAS, OEBR
VM tPZH
VM tPHZ VM 0V VOH -0.3V
OEAS, OEBR
VM tPZL
VM tPLZ VM VOL +0.3V
An, Bn PARITY
An, Bn PARITY
SF01049
SF01050
Waveform 7. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 8. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
1991 Jan 02
9
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1991 Jan 02
10
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
DIP28: plastic dual in-line package; 28 leads (600 mil); long body
SOT117-2
1991 Jan 02
11
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
SO28: plastic small outline package; 28 leads; body width 7.5mm
SOT136-1
1991 Jan 02
12
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
NOTES
1991 Jan 02
13
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05137
Philips Semiconductors
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